`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   10:00:55 10/28/2011
// Design Name:   SNESControllerTest
// Module Name:   C:/Users/Chase/16bitcpu/TestFixtureSNES.v
// Project Name:  CPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: SNESControllerTest
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TestFixtureSNES;

	// Inputs
	reg CLK;
	reg reset;
	reg data;
	
	// Outputs
	wire latch;
	wire pulse;
	wire plyr_input;

	// Instantiate the Unit Under Test (UUT)
	SNESControllerTest uut (
		.CLK(CLK),
		.reset(reset), 
		.latch(latch), 
		.pulse(pulse), 
		.data(data), 
		.plyr_input(plyr_input)
	);

	initial begin
		// Initialize Inputs
		CLK = 0;
		reset = 0;
		data = 0;
		
		// Wait 100 ns for global reset to finish
		#100;
      reset = 1;
		#20
		reset = 0;

		
		// Add stimulus here
			
	end
	

		
	   always begin
		#10 CLK = ~CLK;
		end
      
endmodule

